Design of CMOS op-amp at 1 V
Abstract
Design of CMOS op-amp at 1 V
Incoming article date: 02.03.2015Problems for the design of low-voltage CMOS op-amps are considered: low voltage headroom for signal swings, increase the swing of input and output common-mode signal and sustainability when the feedback. Ways to implement input and output stages of low-voltage CMOS op-amps for technology 0.13 um at 1 V are investigated. The ways of frequency compensation are investigated. According to the results of modeling the best gain and the largest swing of input and output signal have continuous in time common-mode feedback circuit (CMFB) and the proposed two-stage current mirrors op-amp. These op-amps can be applied at a supply voltage ~ 1 V.
Keywords: low-voltage CMOS operational amplifiers (op-amps), the input and output swing, miller-effect frequency compensation