The operation of finding the remainder of division is an arithmetic operation that plays a big role in number theory. The most important role this operation has in the design of devices using, modular arithmetic. Modular arithmetic has high parallelism and is often used with high-dimensional data to speed up computations. When working with modular arithmetic, data of large dimensions (about 128-512 bits) are often used. To find modular representation of data, effective way is needed to find the remainder from the division of multi-digit numbers by the corresponding set of moduli. The article explores the methods for constructing devices for finding the remainder of the division, for large dimensions of input data, in which the divisor p - is a constant and is known at the device design stage. The options for implementing such devices are investigated, their optimal parameters are determined, and the delay and area compared with the Verilog operation "%", both in the VLSI and in the FPGA synthesis.

Keywords: residue number system, remainder of division, modulo operation, cad

The article suggests a technique for automatic segmentation of satellite images on the basis of convolutional neural networks into several classes, such as buildings, rivers, roads, etc. The software implementation of the proposed methodology took the second place in the competition for the segmentation of satellite imagery on the Kaggle platoform in competition: Dstl Satellite Imagery Feature Detection. The article describes how to prepare images for the training of neural network and reveal details for full dataflow and the principles of the traning. The structure of the neural network for segmentation is proposed. The network is built on the basis of UNET with additional BatchNormalization and Dropout layers, based on double convolution blocks. A procedure for cross-evaluation is described to assess the accuracy of the models obtained. The descriptions of algorithms for postprocessing and the technique of segmentation refinement are presented by using an ensemble of several models. A specialized model is proposed for finding objects of small size, such as "cars" and "motorcycles". An overview of other methods used to solve this problem is also given, which were not included in the final solution. In the experimental results it is shown that the efficiency of neural networks in this task is extremely high and it is possible to automatically prepare a layout of the terrain similar to the markup made by human. And thereby it allows to save money, since significant financial resources are being spent on manual marking.

Keywords: convolutional neural nets, sattelite imagery, image segmentation, machine learning, crossvalidation, Jaccard coefficient, UNET network, image classification, computer vision, contest results

Currently, issues of development of power efficient hardware blocks for digital signal processing (DSP) devices gain special importance. This is due to the rapid flourishing of wearable electronics, the Internet of things (IoT), network and telecommunication systems. The key component of many DSP devices is a finite impulse response (FIR) filter. It is not surprising that currently a large number of scientific papers are devoted to the development of power efficient FIR filters. The article proposes an original approach to the issue solution. As a methodological basis, modular arithmetic was chosen, already proven as an effective mathematical apparatus for the development of high-speed DSP devices. Another solution was the use of the FIR filter transposed form and methods for constructing the reduced blocks of the multiconstant multipliers. The experimental part demonstrated the efficiency of the block reduction methods of the multiconstant multiplication from the point of view of the filter power consumption. The article also made recommendations for the use of the proposed methods for specific implementations of the FIR filters.

Keywords: modulo FIR filter, multiconstant multiplier, transposed form, power consumption, dissipated power

The paper presents a method for creating model for combinational circuit implementation in FPGA basis, through its original description. This model represents the equivalent circuit of the FPGA logic elements. The scheme can be used for the calculation of various parameters such as speed, area, power consumption etc. The paper proposes to use this model to assess reliability in relation to the single fault in combinational circuit’s parts or the configuration registers. Furthermore, the resulting equivalent circuit can be modified and re-synthesized in the CAD environment to achieve high levels of resistance to a single event upset. Direct estimation of the masking properties of the logic circuit through its original description is impossible because of substantial change in the structure due to the synthesis process. Evaluation of fault tolerance after place and route is not available due to lack of the necessary tools in modern CAD (Altera Quartus II, Xilinx ISE, Synopsys Synplify). To evaluate the reliability of the project one must create custom FPGA netlist analysis tool and tools for modeling combinational circuits.

Keywords: reliability evaluation, re-synthesis, combinational circuits, FPGA, fault injection.