The paper offers a solution to the general problem of circuit synthesis for n-MOS transistor level band pass filter based on current amplifier with a limited transmission coefficient. The possibility of optimal choice of the parametric compromise. The results of modeling circuit in Cadence Virtuoso environment component-based workflow SGB25VD.

Keywords: CMOS transistor, a band pass filter, a selective amplifier, system on chip, gain, voltage-to-current

  This paper presents a generalized framework level band pass filter used in the construction of broadband active RC filters. The conditions that determine the potential stability of the broadband link and its parameters. A variant of circuit implementation, in which low parametric sensitivity of Q to passive circuit elements is achieved on the basis of its own compensate small-signal parameters of bipolar transistors parameters amplification. The results of computer simulations have confirmed that the principle of self compensate coupling semiconductor can significantly reduce the sensitivity of the parametric parts of the second-order band-pass filters based on existing low technologies.

Keywords: system-on-chip, band pass filter, quality, current amplifier, the sensitivity, bipolar transistor

  The paper discusses the features of their own circuits and mutual compensation circuitry in a differential stage in CMOS transistors. It is shown that their composition can significantly increase the differential gain in symmetric cascades with a dynamic load, significantly reduce common mode gain and extend the range of operating frequencies. As an example, the evolution of the basic concept of a symmetric stage and the results of its simulation in Cadence Virtuoso.

Keywords: micro circuitry, structural synthesis, complex-function blocks, a differential stage, a CMOS transistor, system-on-chip

  The paper discusses architecture of stabilizers, which realize the effect of own noise compensation of reference voltage. Circuits with own compensation of noise allow to reduce the noise in comparison with the classical circuits at a small values of the correction capacitor. A mathematical analysis of the proposed circuit is given. The results are confirmed by computer simulation in Cadence using transistors model of 0.6 um BiCMOS process technology.

Keywords: voltage stabilizer, noise, system on chip, BiCMOS technology, computer modeling, proper compensation

  The paper presents a functional diagram multidifferential operational amplifier, which in contrast to conventional operational amplifiers, has some inverting and non-inverting inputs, and provides a relatively high input voltage limit. Application of basic common-mode feedback signal allowed increasing CMRR voltage on both channels. The use of additional passive components in the emitter circuit of the multidifferential cascade possible to increase the voltage limit of the operational amplifier, the rate of increase of its output voltage to provide high accuracy ratio of the transmission channel and to improve the stability of the corresponding parameters of measuring devices based on multidifferential operational amplifier.

Keywords: system-on-chip, input stage, radiation, amplifier, analog-to-digital converter, bipolar transistor, field transistor

Theoretical analysis of constructive and technological restrictions in the avalanche photodiode structure for photon-counting mode is made in this work. It is shown that critical parameters are load resistance and a time constant of a photodiode internal capacity recharge. For decreasing this time constant one needs size restriction of separate section of the photodiode and association of several such sections on a crystal together with registration schemes.

Keywords: Avalanche photodiode, Mode of the account of photons, Constructive-technological restrictions, Model of avalanche breakdown

The contemporary problems of chip manufacturing process in particular for small series are briefly reviewed. The costs optimization methods used for the preparation and launching of chip manufacturing are described in detail. New organization structures for the chip design and production are proposed. The implementation of the manufacturing process of this new type (i.e. “intelligent” production) is reviewed. The main feature of the “intelligent” production is that it takes into account not only essential technological steps but also involves design center and customer service support into the entire scheme describing the whole cycle of manufacturing. The real examples of manufacturing process modification and appropriate recommendations are given.

Keywords: chip for small series, “intelligent” manufacturing process, chip production standard route, MLM route, MPW route, production costs, modification of production route, united order.

The development of semiconductor nanoelectronics industry in the world in terms of globalization is reviewed. The main roadmaps of information technologies development are outlined. The primary method for the costs reduction is the global harmonization of technical solutions (e.g., an international standardization system) which can be achieved through the creation of global alliances. These global alliances lead to partition sectors of the market and the exchange of technological advances and by promoting national programs of information technology development, combining the efforts of public and private sectors. The forecast of the possible development of Nan electronics industry in Russia is given.

Keywords: semiconductor scheme, chip manufacturing, globalization, nanoscale semiconductor devices, information networks, chip design, design methods.

In the present paper we propose a modified approximation of a silicon bipolar transistor, which takes into account the frequency relationship of electromagnetic signals propagation in the substrate. These modifications were implemented because the experimental investigations and crosstalk simulations in the metallization layers of a silicon substrate have showed that the commonly used approximations based on lumped elements are not able to describe properly the mutual influence of signals at gigahertz frequencies. It was shown that the proposed method is suitable for high-frequency analog circuits design and it is based on sparse distribution of circuit elements and additional shielding of high-frequency chains. The reproducibility and stability of the circuit’s parameters is achieved by secondary devices which are added for correction and stabilization.

Keywords: heterostructure bipolar transistors, silicon-germanium base layer, ionizing radiation, simulation of analog cells using substrate influence effect, analog cells parameters stabilization and correction.

The article deals with sonar communication channel, its characteristics, factors affecting the distribution of hydro-acoustic waves in the ocean environment. For video data compression methods are considered digital imaging and design of proposed systems for transmission of digital video signal and a block diagram of the ADC.

Keywords: sonar, hydroacoustic communication channel, the acoustic wave, high-speed ADC.